The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for monitoring and verifying a clock state of a chip.
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits. Although the word signal has a number of other meanings, the term “signal” here is used for “transmitted energy that can carry information”.
A clock signal is produced by a clock generator. Although more complex arrangements are used, the most common clock signal is in the form of a square wave with a 50% duty cycle, usually with a fixed, constant frequency. Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge, or, in the case of double data rate, both in the rising and in the falling edges of the clock cycle.
Most integrated circuits (ICs) of sufficient complexity use a clock signal in order to synchronize different parts of the circuit and to account for propagation delays. As ICs become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult. The preeminent example of such complex chips is the microprocessor, the central component of modern computers, which relies on a clock from a crystal oscillator. The only exceptions are asynchronous circuits such as asynchronous CPUs.
A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit. This technique is often used to save power by effectively shutting down portions of a digital circuit when they are not in use.
The internal clock state of an integrated circuit chip, which may be referred to simply as a chip, is a very important piece of status information which is used to check for the state of the chip before allowing a chip hardware access. Traditionally, the internal clock state has been made available in a passive status value that is automatically returned after any register access. However, newer chips instead require explicit register accesses to read the clock state directly.